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SP6133
TM
Synchronous Buck Controller
FEATURES 5V to 24V Input step down converter Up to 30A output capability Highly integrated design, minimal components UVLO Detects Both VCC and VIN Overcurrent circuit protection with auto-restart Power Good Output, ENABLE Input Maximum Controllable Duty Cycle Ratio up to 92% Wide BW amp allows Type II or III compensation Programmable Soft Start Fast Transient Response HighEfficiency:Greaterthan95%possible Available in Lead Free, RoHS Compliant 6-Pin QFN package External Driver Enable/Disable U.S. Patent #6,922,04
UVIN BST
13 12 GH 11 10 9 8 SWN ISP ISN
VCC
16 GL PGND GND 1 2 3 4 5
15
SP6133
16 Pin QFN 3mm x 3mm
VFB
6
VIN
14 7
COMP
EN
PWRGD
VIN 10-15V GND 3.3V 0-10A GND
DESCRIPTION The SP633 is a synchronous step-down switching regulator controller optimized for high efficiency.Thepartisdesignedtobeespeciallyattractiveforsinglesupplystepdownconversion from 5V to 24V. The SP633 is designed to drive a pair of external NFETs using a fixed300kHzfrequency,PWMvoltagemodearchitecture.ProtectionfeaturesincludeUVLO, thermal shutdown, output short circuit protection, and overcurrent protection with auto restart. The device also features a PWRGD output and an enable input. The SP633 is available in a space saving 6-pin QFN and offers excellent thermal performance. TYPICAL APPLICATION CIRCUIT
C5 0.1uF DBST CVCC 10uF BAT54WS VIN VCC R3 10K POWERGOOD NC PWRGD UVIN EN ENABLE BST GH SWN SC5018-2R7M 2.7uH, 15A, 4.1mOhm MB, Si4320DY 4 mOhm, 30V CBST 0.1uF MT, Si4394DY 9.75 mOhm, 30V C1 22uF C2 22uF
VOUT
C3 100uF C4 100uF
SP6133
GL
RS1 5.11K
RS2 5.11K
GND
PGND
ISP ISN CSP 6.8nF CSS 47nF RZ3 1K CS 0.1uF
COMP CP1 39 pF
VFB
SS
R1 68.1K, 1%
CZ3 560pF CF1 22pF CZ2 1500pF RZ2 23.2K
R2 21.5K, 1%
Note: Die attach paddle is internally connected to GND.
Oct 24-06 Rev L SP633 Synchronous Buck Controller (c) 2006 Sipex Corporation
SS
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections ofthespecificationsbelowisnotimplied.Exposuretoabsolutemaximum rating conditions for extended periods of time may affect reliability. VCC .................................................................................................. 6V VIN .............................................................................................. 24.5V BST................................................................................................ 30V BST-SWN ........................................................................................ 7V SWN .................................................................................-2V to 24.5V GH ..........................................................................-0.3V to BST+0.3V GH-SWN.......................................................................................... 6V All other pins ............................................................-0.3V to VCC+0.3V PeakOutputCurrent<10s GH,GL ............................................................................................. 2A Storage Temperature ................................................... -65Cto150C Power Dissipation ........................................................................... W ESD Rating ........................................................................... 2kV HBM Thermal Resistance.............................................................. 41.9C/W
Unlessotherwisespecified:-40CELECTRICAL SPECIFICATIONS
PARAMETER
QUIESCENT CURRENT
VIN Supply Current VCC Supply Current BST Supply Current PROTECTION: UVLO VCC UVLO Start Threshold VCC UVLO Hysteresis UVIN Start Threshold UVIN Hysteresis VIN Start Threshold VIN Hysteresis Enable Pullup Current ErrorAmplifierReference ErrorAmplifierReference Over Line & Temperature COMP Sink Current COMP Source Current VFB Input Bias Current COMP Common Mode Output Range COMP Pin Clamp Voltage
MIN
TYP MAX UNITS CONDITIONS
.5 .5 0.2 3.0 3.0 0.4 4.5 250 2.65 400 0.0 mA mA mA V mV V mV V mV A 0.808 0.82 230 -70 00 3.2 3.8 V V A A nA V V VFB = 0.7V Apply voltage to UVIN pin Apply voltage to UVIN pin UVIN Floating UVIN Floating Apply voltage to EN pin 2xGainConfig. VFB = V (no switching) VFB = V (no switching) VFB = V (no switching)
4.00 50 2.35 200 9.0
4.25 200 2.50 300 9.5 300 0.4
ERROR AMPLIFIER REFERENCE
0.792 0.800 0.788 0.800 70 -230 .9 3.2 50 -50 50 3.0 3.5
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SP633 Synchronous Buck Controller
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Unlessotherwisespecified:-40CELECTRICAL SPECIFICATIONS
PARAMETER
Ramp Offset Ramp Amplitude GH Minimum Pulse Width Maximum Controllable Duty Ratio Maximum Duty Ratio InternalOscillatorFrequency
MIN
.7 0.80 92 00 255 -6 .0
TYP
2.0 .0 50
MAX UNITS CONDITIONS
2.3 .20 00 V V ns % % Guaranteed by design TA=25C
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
300 -0 2.0
345 -4 3.0
kHz A mA Fault Present VIN = 6 to 23V, ILOAD = 0mA to 30mA IVCC = 30mA
TIMERS: SOFTSTART
SSChargeCurrent: SSDischargeCurrent:
VCC LINEAR REGULATOR
VCC Output Voltage Dropout Voltage 4.6 250 -0 5.0 500 -7.5 2.0 .0 5.4 750 -5 4.0 0 V mV % % mA VFB = 0.7V, VPWRGD = 0.2V Measured VREF (0.8V) - VFB Measured ISP - ISN
POWER GOOD OUTPUT
Power Good Threshold Power Good Hysteresis Power Good Sink Current
PROTECTION: SHORT CIRCUIT & THERMAL
Short Circuit Threshold Voltage Overcurrent Threshold Voltage ISP, ISN Common Mode Range Hiccup Timeout Thermal Shutdown Temperature Thermal Hysteresis 0.2 54 0 85 35 220 45 0 0.25 60 0.3 66 3.3 270 55 V mV V ms C C Guaranteed by design
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Unlessotherwisespecified:-40CELECTRICAL SPECIFICATIONS
PARAMETER
GH & GL Rise Times GH & GL Fall Times GL to GH Non Overlap Time SWN to GL Non Overlap Time GH & GL Pull Down Resistance Driver Pull Down Resistance Driver Pull Up Resistance
MIN TYP MAX UNITS
35 30 45 25 5 50 .5 2.5 50 40 70 40 85 .9 3.9 ns ns ns ns K

CONDITIONS
Measured 0% to 90% Measured 90% to 0% GH & GL Measured at 2.0V Measured SWN = 00mV to GL = 2.0V
OUTPUT: NFET GATE DRIVERS
BLOCk DIAGRAM
VCC
5
COMP SS
NON SYNC. STARTUP COMPARATOR GL HOLD OFF
VFBINT 4 VCC VCC 10 uA SOFTSTART INPUT SS 8 0.1V VPOS POS REF Gm FAULT Gm ERROR AMPLIFIER
1.6 V
PW M LOO P
RESET DOMINANT R Q FAULT S QPWM
13 BST
VFB
12 GH
SYNCHRONOUS DRIVER
11 SWN 1 GL
FAULT RAMP = 1V
300 kHZ 2 PGND
CLK CLOCK PULSE GENERATOR
2.8 V VCC 16 REFERENCE CORE 0.8V REF OK
1.3 V VCC 1 uA ENABLE EN 6 1.7V ON 1.0V OFF COMPARATOR
4.25 V ON 4.05 V OFF VCC UVLO
POWER FAULT
FAULT
THERMAL SHUTDOWN 145C ON 135C OFF
SET DOMINANT S Q HICCUP FAULT 3 GND
5V LINEAR REGULATOR VPOS VIN 14 VFBINT 140K UVIN 15 2.50 V ON 2.20 V OFF 50K
0.25V
SHORT CIRCUIT DETECTION
R
CLK 220ms Delay OVER CURRENT DETECTION COUNTER CLR REF OK Power Good VFB 0.74 V ON 0.72 V OFF 7 PWRGD
VIN UVLO 10 ISP 9 ISN
60 mV
UVLO COMPARATORS
THERMAL AND O VER CURRENT PRO TECTION
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SP633 Synchronous Buck Controller
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PIN PIN # NAME 2 3 4 5 6 7 8 9 0 2 3 4 5 6 GL PGND GND VFB COMP EN PWRGD SS ISN ISP SWN GH BST VIN UVIN VCC
DESCRIPTION
PIN DESCRIPTION
High current driver output for the low side NFET switch. It is always low if GH is high or during a fault. Resistor pull down ensures low state at low voltage. Ground Pin. The power circuitry is referenced to this pin. Return separately from other ground traces to the (-) terminal of Cout. Ground pin. The control circuitry of the IC is referenced to this pin. FeedbackVoltageandShortCircuitDetectionpin.ItistheinvertinginputoftheErrorAmplifier and serves as the output voltage feedback point for the Buck Converter. The output voltage is sensed and can be adjusted through an external resistor divider. Whenever VFB drops 0.25V below the positive reference, a short circuit fault is detected and the IC enters hiccup mode. OutputoftheErrorAmplifier.Itisinternallyconnectedtothenon-invertinginputofthePWM comparator.Anoptimalfiltercombinationischosenandconnectedtothispinandeither ground or VFB to stabilize the voltage mode loop. Enable Pin. Pulling this pin below 0.4V will place the IC into sleep mode. This pin is internally pulled to VCC with a A current source. Power Good Output. This open drain output is pulled low when VOUT is outside of the regulation. Connect an external resistor to pull high. Soft Start/Fault Flag. Connect an external capacitor between SS and GND to set the soft start rate based on the 0A source current. The SS pin is held low via a mA (min) current during all fault conditions. Negative Input for the Sense Comparator. There should be a 60mV offset between PSENSE and NSENSE. Offset accuracy +0%. Positive Input for the Inductor Current Sense. Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at the junction between the two external power MOSFET transistors. High current driver output for the high side NFET switch. It is always low if GL is high or during a fault. High side driver supply pin. Connect BST to the external boost diode and capacitor as shown in the Application Schematic of page . High side driver is connected between BST pin and SWN pin. Supply Input -- supplies power to the internal LDO. Under Voltage lock-out for VIN voltage. Internally has a resistor divider from VIN to ground. Can be overridden with external resistors. Output of the Internal LDO. If VIN is less than 5V then Vcc should be powered from an external 5V supply.
Note: Die attach paddle is internally connected to GND. THEORY OF OPERATION
General Overview
The SP6133 is a fixed frequency, voltage mode, synchronous PWM controller optimizedforhighefficiency.Theparthasbeen designed to be especially attractive for single supply input voltages ranging between 5V and 24V. The heart of the SP633 is a wide bandwidth transconductanceamplifierdesignedtoaccommodate Type II and Type III compensaOct 24-06 Rev L
tion schemes. A precision 0.8V reference present on the positive terminal of the error amplifier permits the programming of the output voltage down to 0.8V via the VFB pin. The output of the error amplifier, COMP, compared to a V peak-to-peak ramp is responsible for trailing edge PWM control. This voltage ramp and PWM control logic are governed by the internal oscillator that accuratelysetsthePWMfrequencyto300kHz.
(c) 2006 Sipex Corporation
SP633 Synchronous Buck Controller
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THEORY OF OPERATION The SP6133 contains two unique control features that are very powerful in distributed applications. First, non-synchronous driver control is enabled during start up to prohibit the low side NFET from pulling down the output until the high side NFET has attempted to turn on. Second, a 00% duty cycle timeout ensures that the low side NFET is periodically enhanced during extended periods at 00% duty cycle. This guarantees the synchronized refreshing of the BST capacitor during very large duty ratios. The SP633 also contains a number of valuable protection features. A programmable input UVLO allows a user to set the exact value at which the conversion voltage is at a safe point to begin down conversion, and an internal VCC UVLO ensures that the controller itself has enough voltage to properly operate. Other protection features include thermal shutdown and short-circuit detection. In the event that either a thermal, short-circuit, or UVLO fault is detected, the SP633 is forced into an idle state where the output drivers are held off for a finiteperiodbeforeare-startisattempted.
Soft Start
and the 0.8V reference voltage. Therefore, theexcesscurrentsourcecanberedefinedas: IVIN, x = COUT * VOUT *
Hiccup
0A (CSS *0.8V)
Upon the detection of a power, thermal, or short-circuit fault, the SP633 is forced into an idle state for a minimum of 200ms. The SS and COMP pins are immediately pulled low, and the gate drivers are held off for the duration of the timeout period. Power and thermal faults have to be removed before a restart may be attempted, whereas, a shortcircuit fault is internally cleared shortly after the fault latch is set. Therefore, a restart attempt is guaranteed every 200ms (typical) as long as the short-circuit condition persists. A short-circuit detection comparator has also been included in the SP633 to protect against the accidental short or severe build up of current at the output of the power converter. This comparator constantly monitors theinputstotheerroramplifier,andifthe VFB pin ever falls more than 250mV (typical) below the voltage reference, a short-circuit fault is set. Because the SS pin overrides the internal 0.8V reference during soft start, the SP633 is capable of detecting short-circuit faults throughout the duration of soft start as well as in regular operation.
Error Amplifier & Voltage Loop
"Soft Start" is achieved when a power converter ramps up the output voltage while controlling the magnitude of the input supply source current. In a modern step down converter, ramping up the non-inverting input oftheerroramplifiercontrolssoftstart.Asa result,excesssourcecurrentcanbedefined asthecurrentrequiredtochargetheoutput capacitor IVIN, x = Cout *Vout TSoft-start
The SP633 provides the user with the option to program the soft start rate by tying a capacitor from the SS pin to GND. The selection of this capacitor is based on the 0A pull up current present at the SS pin
Oct 24-06 Rev L
As stated before, the heart of the SP633 voltage error loop is a high performance, widebandwidthtransconductanceamplifier. Because of the amplifier's current limited (+00A) transconductance, there are many ways to compensate the voltage loop or to control the COMP pin externally. If a simple, singlepole,singlezeroresponseisrequired, then compensation can be as simple as an RC circuit to ground. If a more complex compensationisrequired,thentheamplifier hasenoughbandwidth(45Cat4MHz) and enough gain (60 dB) to run Type III
(c) 2006 Sipex Corporation
SP633 Synchronous Buck Controller
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THEORY OF OPERATION compensationschemeswithadequategain andphasemarginsatcrossoverfrequencies greater than 200 kHz. The common mode output of the error amplifier(COMP)is0.9Vto2.2V.Therefore,the PWM voltage ramp has been set between .0V and 2.0V to ensure proper 0% to 00% duty cycle capability. The voltage loop also includes two other very important features. One is a non-synchronous start up mode. Basically, the GL driver cannot turn on unless the GH driver has attempted to turn on or the SS pin has exceeded .7V. This feature prevents the controller from "dragging down" the output voltage during startup or in fault modes. The second feature is a 00% duty cycle timeout that ensures synchronized refreshing of the BST capacitor at very high duty ratios. In the event that the GH driver is on for 20 continuous clock cycles, a reset is giventothePWMflipflophalfwaythrough the 20th cycle. This forces GL to rise for the remainder of the cycle, in turn refreshing the BST capacitor.
Gate Drivers Over-Current Protection
Over-current is detected by monitoring a differential voltage across the output inductorasshowninfigure1.Inputstoanovercurrent detection comparator, set to trigger at 60 mV nominal, are connected to the inductor as shown. Since the average voltage sensed by the comparator is equal to the product of inductor current and inductor DC resistance (DCR) then Imax = 60mV / DCR. Solving thisequationforthespecificinductorincircuit , Imax = 4.6A. When Imax is reached, a 220 ms time-out is initiated, during which top and bottom drivers are turned off. Following the time-out, a restart is attempted. If the fault condition persists, then the timeout is repeated (referred to as hiccup).
SP613X
SWN L = 2.7uH, DCR = 4.mOhm
Vout
RS 5.K
RS2 5.K
The SP633 contains a pair of powerful 2 Pull-up and .5 Pull-down drivers. These state-of-the-art drivers are designed to drive an external NFET capable of handling up to 30A. Rise, fall, and non-overlap times have all been minimized to achieve maximum efficiency.All drive pins GH, GL, & SWN are monitored continuously to ensure that only one external NFET is ever on at any given time.
Thermal & Short-Circuit Protection
ISP ISN CSP 6.8nF CS 0.uF
Figure 1: Over-current detection circuit
Because the SP633 is designed to drive large NFETs running at high current, there is a chance that either the controller or power converter will become too hot. Therefore, an internalthermalshutdown(145C)hasbeen included to prevent the IC from malfunctioning at extreme temperatures.
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SP633 Synchronous Buck Controller
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APPLICATION INFORMATION
Increasing the Current Limit
RS3 = RS2 * [Vout - 60mV + (IMAX*DCR)]............(2) 60mV - (IMAX * DCR) Asanexample:forImax of 2A and Vout of 3.3V, calculated RS3 is .5M.
SP613X
SWN L = 2.7uH, DCR = 4.mOhm
If it is desired to set Imax > {60mV / DCR} (in this case larger than 4.6A), then a resistor RS3 shouldbeaddedasshowninfigure2. RS3 forms a resistor divider and reduces the voltage seen by the comparator. Since:60mV Imax * DCR = RS3 {RS + RS2 + RS3} SolvingforRS3weget: RS3 = [60mV *(RS + RS2)] [(Imax * DCR) - 60mV] ..........()
Vout
RS 5.K
RS2 5.K
Asanexample:ifdesiredImax is 7A, then RS3 = 63.4K.
SP613X
SWN L = 2.7uH, DCR = 4.mOhm
ISP ISN CSP 6.8nF CS 0.uF RS3 .5MOhm
Vout
RS 5.K RS3 63.4K CSP 6.8nF CS 0.uF
RS2 5.K
Figure 3- Over-current detection circuit for Imax < {60mV / DCR}
Power MOSFET Selection
ISP ISN
Figure 2- Over-current detection circuit for Imax > 60mV / DCR
Decreasing the Current Limit
There are four main criterion in selecting PowerMOSFETsforbuckconversion: Voltage rating BVdss On resistance Rds(on) Gate-to-drain charge Qgd Package type

IfitisrequiredtosetImax<{60mV/DCR}, a resistorisaddedasshowninfigure3.RS3 increases the net voltage detected by the current-sense comparator. Voltage at the positive and negative terminal of comparatorisgivenby: VSP = Vout + (Imax * DCR) VSN = Vout * {RS3 / (RS2 +RS3)} Sincethecomparatoristriggeredat60mV: VSP-VSN = 60 mV Combiningtheaboveequationsandsolving for RS3:
Oct 24-06 Rev L
In order to better illustrate the MOSFET selection process, the following buck converter design example will be used: Vin = 2V, Vout = 3.3V, Iout = 0A, f = 300KHz, DCR = 4.5m(inductorDCresistance),efficiency = 94% and Ta=40C. Select the voltage rating based on maximum input voltage of the converter. A commonly used practice is to specify BVdss at least twice the maximum converter input voltage. This is done to safeguard against switching transients that may break down the MOSFET. For converters with Vin of less than 0V, a 20VratedMOSFETissufficient.Forconvert(c) 2006 Sipex Corporation
SP633 Synchronous Buck Controller
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APPLICATION INFORMATION ers with 0-5Vin, as in the above example, select a 30V MOSFET. The calculation of Rds(on) for Top and Bottom MOSFETs is interrelated and can be done usingthefollowingprocedure: ) Calculate the maximum permissible power dissipation P(dissipation) based on required efficiency. The converter in the above example should deliver an output power Pout = 3.3Vx0A = 33W. For a target efficiencyof94%,inputpowerPin is given by Pin = Pout/0.94 = 35.W. Maximum allowablepowerdissipationisthen: P(dissipation) = Pin - Pout = 2. W 2) Calculate the total power dissipation in top and bottom MOSFETs P(mosFEt) by subtracting inductor losses from P(dissipation) calculated in step . To simplify, disregard core losses; then PL = I2rms *DCR *.4, where .4 accounts for the increase in DCR at operating temperature. For the above example PL=0.63W.Then: P(MOSFET) = 2.W - 0.63W = .47W. 3) Calculate Rds(on) of the bottom MOSFET by allocating 40% of calculated losses to it. 40%dissipationallocationreflectsthefact that the the top MOSFET has essentially no switching loss. Then P(bottom) = 0.4x.47W = 0.59W. Rds(on) = P/(I2rms *.5) where Irms = Iout * {-(Vout/Vin)}0.5 and .5 accounts for the increase in Rds(on) at the operating temperature.Then: Rds(on) = = 5.4 m. 4) Allocate 60% of the calculated losses to the top MOSFET, P(top) = 0.6x.47 = 0.88W. Assume conduction losses equal to switching losses, then P = 0.5x0.88W = 0.44W. Since it operates at the duty cycle of D=Vin/Vout; then:
Oct 24-06 Rev L
Rds(on) =
P
[I
2
out
* (Vout/Vin) * .5]
= 0.7 m. Gate-to-drain charge Qgd for the top MOSFET needs to be specified. A simplified expressionforswitchinglossesis: Ps = Iout * Vin * f * Vin + Iout
dv/dt
{
where dv/dt and di/dt are the rates at which voltage and current transition across the top MOSFET respectively, and f is the switching frequency.Voltageswitchingtime(Vin /dv/dt) is related to Qgd:
di/dt
}
...................(3)
(Vin /dv/dt) = Qgd/Ig............................... (4)
where Ig is Current charging the gate-to-drain capacitance.Itcanbecalculatedfrom: Ig = (VdrivE-VgatE)/RdrivE......................(5) where VdrivE is the drive voltage of the SP633 top driver minus the drop across the boost diode (approximately 4.5V); VgatE is thetopMOSFET'sgatevoltagecorresponding to Iout (assume 2.5V) and RdrivE is the internal resistance of the SP633 top driver (assume 2 average for turn-on and turn-off). Substitutingthesevaluesinequation(5)we get Ig = A. Substituting for Iginequation (4), we get (Vin /dv/dt) = Qgd. Substituting for (Vin /dv/dt)inequation(3)wehave: Ps = Iout * Vin * f * {Qgd + (Iout / di/dt)} Solving for Qgdweget: Qgd =
P
[{I2out * (-Vout/Vin)} * .5]
{ Iout * Ps * f Vin
_ Iout .............. (6)
di/dt
}
Di/dt is usually limited by parasitic DC-Loop Inductance (Lp) according to di/dt = Vin/Lp. Lp is due to wiring and PCB traces connecting input capacitors and switching MOSFETs.
(c) 2006 Sipex Corporation
SP633 Synchronous Buck Controller
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APPLICATION INFORMATION For typical Lp of 2nH and Vin of 2V, di/dt is1A/ns.Substitutingfordi/dtinequation(6) we get Qgd = 2 nC. In selecting a package type, the main considerations are cost, power/current handling capability and space constraints. A larger package in general offers higher power and current handling at increased cost. Package selection can be narrowed down by calculatingtherequiredjunction-to-ambientthermal resistance ja: ja = {Tj(max) - Ta(max)} / P(max)............. (7) resistor. During startup, output regulates when Soft Start (SS) reaches 0.8V (the reference voltage). PWRGD is enabled when SS reaches .6V. PWRGD output can be used as a "Power on Reset". The simplest way to adjust delay of the "Power on Reset" signal with respect to Vout in regulation is with the Soft Start Capacitor (Css)andisgivenby: Css = (Iss * Tdelay)/0.8 where Iss is the Soft Start charge current (0A nominal).
Under Voltage Lock Out (UVLO)
Where:Tj(max) is the die maximum temperature rating, Ta(max)is maximum ambient temperature, and P(max) is maximum power dissipated in the die. It is common practice to add a guard-band of 25C to the junction temperature rating. Following this convention, a 150C rated MOSFETwillbedesignedtooperateat125C (i.e., Tj(max) =125C).P(max) = 0.88W (from section 4) and Ta(max) =40Casspecifiedin thedesignexample.Substitutinginequation (7) we get ja=96.6C/W. For the top MOSFET, we now have determined the following requirements; BVdss = 30V, Rds(on) = 0.7m, Qgd = 2 nC and ja < 96.6C/W.AnSO-8MOSFETthatmeetsthe requirementsisVishay-Siliconix'sSi4394DY; BVdss = 30V, Rds(on) = 9.75m @ Vgs = 4.5V, Qgd = 2.nC and ja=90C/W. ThebottomMOSFEThastherequirements of BVdss = 30V and Rds(on) = 5.4m. VishaySiliconix'sSi4320DYmeetstherequirements; BVdss = 30V, Rds(on) = 4m @ Vgs = 4.5V.
Power Good
The SP633 has two separate UVLO comparators to monitor the bias (Vcc) and Input (Vin) voltages independently. The Vcc UVLO is internally set to 4.25V. The Vin UVLO is programmable through UVin pin. When UVIN pin is greater than 2.5V the SP633 is permitted to start up pending the removal of all other faults. A pair of internal resistors isconnectedtoUVINasshowninfigure4. Therefore without external biasing the Vin start threshold is 9.5V. A small capacitor may berequiredbetweenUVINandGNDtofilter out noise. For applications with Vin of 5V or 3.3V, connect UVIN directly to Vin.
SP613X
VIN
R4 UVIN
40K
R5 GND
2.5V ON 2.2V OFF 50K
+ -
Figure 4- Internal and external bias of UVIN To program the Vin start threshold, use a pair of external resistors as shown. If external resistors are an order of magnitude smaller than internal resistors, then the Vin start thresholdisgivenby: Vin(start) = 2.5 * (R4+R5)/R5................ (8)
(c) 2006 Sipex Corporation
Power Good (PWRGD) is an open drain output that is pulled low when Vout is outside regulation. The PWRGD pin can be connected to VCC with an external 0K
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SP633 Synchronous Buck Controller
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APPLICATION INFORMATION Forexample,ifitisrequiredtohaveaVin start threshold of 7V, then let R5 = 5K and usingequation(8)wegetR4=9.09K.
Inductor Selection
There are many factors to consider in selecting the inductor including cost, efficiency, size and EMI. In a typical SP633 circuit, the inductor is chosen primarily for value, saturation current and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. Low inductor values provide the smallest size, but cause large ripple currents,poorefficiencyandneedmoreoutput capacitance to smooth out the larger ripple current. The inductor must also be able to handle the peak current at the switching frequencywithoutsaturating,andthecopper resistance in the winding should be kept as low as possible to minimize resistive power loss. A good compromise between size, loss and cost is to set the inductor ripple current to be within 20% to 40% of the maximum output current. The switching frequency and the inductor operating point determine the inductor value asfollows: Vout * (Vin(max) - Vout) Vin(max) * Fs * Kr * Iout(max) where: Fs=switchingfrequency Kr = ratio of the ac inductor ripple current to the maximum output current L=
.
and provide low core loss at the high switchingfrequency.Lowcostpowderedironcores have a gradual saturation characteristic but can introduce considerable AC core loss, especially when the inductor value is relatively low and the ripple current is high. Ferrite materials, on the other hand, are more expensive and have an abrupt saturation characteristic with the inductance dropping sharply when the peak design current is exceeded. Nevertheless, they are preferred athighswitchingfrequenciesbecausethey present very low core loss and the design only needs to prevent saturation. In general, ferrite or molypermalloy materials are the better choice for all but the most cost sensitive applications. Thepowerdissipatedintheinductorisequal to the sum of the core and copper losses. To minimize copper losses, the winding resistance needs to be minimized, but this usually comes at the expense of a larger inductor.Corelosseshaveamoresignificant contribution at low output current where the copper losses are at a minimum, and can typically be neglected at higher output currents where the copper losses dominate. Core loss information is usually available from the magnetic vendor. The copper loss in the inductor can be calculatedusingthefollowingequation: PL(cu) = I2L(rms) * Rwinding where IL(rms) is the RMS inductor current that canbecalculatedasfollows: IL(rms) =
Thepeaktopeakinductorripplecurrentis: Ipp = Vout * (Vin(max) - Vout) Vin(max) * Fs * L
Oncetherequiredinductorvalueisselected, the proper selection of core material is based onpeakinductorcurrentandefficiencyrequirements.Thecoremustbelargeenough not to saturate at the peak inductor current IpEak = Iout(max) + Ipp/2
Oct 24-06 Rev L
Iout(max) *
.
.
+ * 3
Ipp { Iout(max) }
2
SP633 Synchronous Buck Controller
(c) 2006 Sipex Corporation
APPLICATION INFORMATION
Output Capacitor Selection
The required ESR (Equivalent Series Resistance) and capacitance drive the selectionofthetypeandquantityoftheoutput capacitors. The ESR must be small enough that both the resistive voltage deviation due to a step change in the load current and the output ripple voltage do not exceed the tolerance limits expected on the output voltage. During an output load transient, the output capacitor must supply all the additional current demanded by the load until the SP633 adjusts the inductor current to the new value. Therefore, the capacitance must be large enough so that the output voltage is held up while the inductor current ramps up or down to the value corresponding to the new load current. Additionally, the ESR in the output capacitor causes a step in the output voltage equaltothecurrent.Becauseofthefasttransient response and inherent 00% and 0% duty cycle capability provided by the SP633 when exposed to output load transients, the output capacitor is typically chosen for ESR, not for capacitance value. Theoutputcapacitor'sESR,combinedwith the inductor ripple current, is typically the main contributor to output voltage ripple. The maximum allowable ESR required to maintain a specified output voltage ripple canbecalculatedby: RESR < Vout ipk-pk where: Vout = Peak to Peak Output Voltage Ripple ipk-pk = Peak to Peak Inductor Ripple Current The total output ripple is a combination of the ESR and the output capacitance value andcanbecalculatedasfollows: Vout =
.
.
(IppREsr)2 +
{
Ipp * (1-d) Cout * Fs
}
2
where: Fs=SwitchingFrequency D = Duty Cycle Cout = Output Capacitance Value
Input Capacitor Selection
The input capacitor should be selected for ripple current rating, capacitance and voltage rating. The input capacitor must meet the ripplecurrentrequirementimposedbythe switching current. In continuous conduction mode, the source current of the high-side MOSFETisapproximatelyasquarewave of duty cycle Vout/VIN. Most of this current is supplied by the input bypass capacitors. The RMS value of input capacitor current is determined at the maximum output current and under the assumption that the peak to peak inductor ripple current is low, it is givenby: Icin(rms) = Iout(max) * D * (-D)
Schottky Diode Selection
When paralleled with the bottom MOSFET, an optional Schottky diode can improve efficiency and reduce noise. Without this Schottky diode, the body diode of the bottom MOSFET conducts the current during the non-overlap time when both MOSFETs are turned off. Unfortunately, the body diode has high forward voltage and reverse recovery problems. The reverse recovery of the body diode causes additional switching noise when the diode turns off. The Schottky diode alleviates these sources of noise and additionallyimprovesefficiencythankstoits low forward voltage. The reverse voltage acrossthediodeisequaltoinputvoltage, and the diode must be able to handle the peak current equal to the maximum load current.
(c) 2006 Sipex Corporation
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APPLICATION INFORMATION The power dissipation of the Schottky diode isdeterminedby: PDIODE = 2 * VF * Iout * TNOL * FS where: TNOL = non-overlap time between GH and GL. VF = forward voltage of the Schottky diode.
Loop Compensation Design
transient response, but often jeopardizes the system stability. Crossover frequency should be higher than the ESR zero but less than 1/5 of the switching frequency. The ESR zero is contributed by the ESR associated with the output capacitors and canbedeterminedby:
z(Esr) =
2 * Cout * REsr
The open loop gain of the whole system can be divided into the gain of the error amplifier,PWMmodulator,buckconverteroutput stage, and feedback resistor divider. In ordertocrossoverattheselectedfrequency FCO,thegainoftheerroramplifierhasto compensate for the attenuation caused by therestoftheloopatthisfrequency. The goal of loop compensation is to manipulateloopfrequencyresponsesuchthatits gain crosses over 0db at a slope of -20db/ dec.Thefirststepofcompensationdesign istopicktheloopcrossoverfrequency.High crossover frequency is desirable for fast
Type III Voltage Loop Compensation GAMP (s) Gain Block VREF (Volts)
The next step is to calculate the complex conjugate poles contributed by the LC outputfilter,
p(Lc) =
2 *
L * COUT
When the output capacitors are of a Ceramic Type,theSP6133EvaluationBoardrequires a Type III compensation circuit to give a phase boostof180inordertocounteracttheeffects of an under damped resonance of the output filteratthedoublepolefrequency.
PWM Stage GPWM Gain Block VIN VRAMP_PP
2
Output Stage GOUT (s) Gain Block (SRESRCOUT+ 1) [S LCOUT+S(RESR+RDC) COUT+1]
+ _
(SRz2Cz2+1)(SR1Cz3+1) SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
VOUT (Volts)
Notes: RESR = Output Capacitor Equivalent Series Resistance. RDC = Output Inductor DC Resistance. VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage. Condition: Cz2 >> Cp1 & R1 >> Rz3 Output Load Resistance >> RESR & RDC Voltage Feedback GFBK Gain Block R2 V (R1 + R2) or VREF VOUT
FBK Figure 5: SP6133 Voltage (Volts) Definitions: Mode Control Loop with REsr=OutputCapacitorEquivalentSeriesResistance Loop Dynamic Rdc = Output Inductor DC Resistance Vramp _ pp = SP633 internal RAMP Amplitude Peak to Peak Voltage
Oct 24-06 Rev L SP633 Synchronous Buck Controller (c) 2006 Sipex Corporation
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APPLICATION INFORMATION
Gain (dB)
Error Amplifier Gain Bandwidth Product Condition: CZ2 >> CP1, R1 >> RZ3
20 Log (RZ2/R1)
1/6.28 (RZ3) (CZ3)
1/6.28 (RZ2) (CP1)
1/6.28(RZ2) (CZ2)
1/6.28 (R1) (CZ3)
1/6.28 (R1) (CZ2)
Frequency (Hz)
Figure 6: Bode Plot of Type III Error AmplifierCompensation Note:LoopCompensationcomponentcalculationsdiscussedinthis DatasheetcanbequicklyiteratedwiththeTypeIIILoopCompensation Calculatoronthewebat: www.sipex.com/files/Application-Notes/TypeIIICalculator.xls
INDUCTORS - SURFACE MOUNT Manufacturer/Part No.
Inter-Technical SC5018-2R7M
Inductance (uH) 2.7
Series R mOhms 4.10
Isat (A) 15.0
Inductor Specification Size LxW(mm) Ht.(mm) 12.6x12.6 4.5
Inductor Type
Shielded Ferrite Core
Manufacturer Website www.inter-technical.com Manufacturer Website www.tdk.com www.tdk.com Manufacturer Website www.vishay.com www.vishay.com
CAPACITORS - SURFACE MOUNT Manufacturer/Part No.
TDK C3225X7R1C226M TDK C3225X5R0J107M
Capacitance (uF) 22 100
ESR ohms (max) 0.005 0.005
Capacitor Specification Ripple Current Size Voltage Capacitor (A) @ 45C LxW(mm) Ht.(mm) (V) Type 4.00 3.2x2.5 2.0 16.0 X7R Ceramic 4.00 3.2x2.5 2.5 6.3 X5R Ceramic MOSFETS - SURFACE MOUNT MOSFET Specification ID Current Qg Voltage (A) nC (Typ) nC (Max) (V) 14 12.5 30 22 45 70 30
Manufacturer/Part No.
Vishay Si4394DY Vishay Si4320DY
MOSFET N-Channel N-Channel
RDS(on) m (max) 9.75 4
Foot Print SO-8 SO-8
Note: Components highlighted in bold are those used on the SP6133 Evaluation Board.
Table 1. Input and Output Stage Components Selection Charts
Oct 24-06 Rev L SP633 Synchronous Buck Controller (c) 2006 Sipex Corporation
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APPLICATION INFORMATION
96 94 92 90 88 86 84 0.0
SP6133 Efficiency vs. Iout @ Vin=12V, Vout=3.3V
3.340 3.338 3.336 3.334 3.332 3.330
SP6133 Load Regulation Vin=12V
2.0
4.0 6.0 Iout (A)
8.0
10.0
0.0
2.0
4.0
6.0
8.0
10.0
Iout (A)
Figure 7: Efficiency vs. Iout, Vin = 12V
Figure 8: Load Regulation, 12V
98 96 94 92 90 0.0
SP6133 Efficiency vs. Iout @ Vin=5V, Vout=3.3V
3.335 3.330 3.325 3.320 3.315 3.310 3.305 3.300
SP6133 Load Regulation Vin=5V
2.0
4.0 6.0 Iout (A)
8.0
10.0
0.0
2.0
4.0
6.0
8.0
10.0
Iout (A)
Figure 9: Efficiency vs. Iout, Vin = 5V
Figure 10: Load Regulation, 5V
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APPLICATION INFORMATION
VIN
C5 0.1uF DBST CVCC 10uF BAT54WS VIN R4 9.09K, 1% VCC R3 10K PWRGD UVIN EN ENABLE BST GH SWN SC5018-2R7M 2.7uH, 15A, 4.1mOhm MB, Si4320DY 4 mOhm, 30V CBST 0.1uF MT, Si4394DY 9.75 mOhm, 30V C1 22uF C2 22uF
7-15V
GND
VOUT
C3 100uF C4 100uF
POWERGOOD
SP6133
GL
R5 5K, 1%
RS1 5.11K
RS2 5.11K
GND
3.3V 0-10A GND
PGND
ISP ISN CSP 6.8nF CSS 47nF RZ3 1K CS 0.1uF
COMP CP1 39 pF
VFB
SS
R1 68.1K, 1%
CZ3 560pF CF1 22pF CZ2 1500pF RZ2 23.2K
R2 21.5K, 1%
Figure 11: SP6133 circuit showing wide input range
VIN
C5 0.1uF DBST CVCC 10uF BAT54WS VIN VCC R3 10K POWERGOOD PWRGD UVIN EN ENABLE BST GH SWN INTER-TECHNICAL, SC4015-R75M 0.75uH, 20A, 3.25mOhm MB, Si4304DY 3.7 mOhm, 30V CBST 0.1uF MT, Si4304DY 3.7 mOhm, 30V
VAUX=5V
C1 100uF
C2 100uF
3-3.6V
GND
VOUT
C3 68uF C4 68uF
SP6133
GL
RS1 5.11K
RS2 5.11K
GND
1.8V 0-10A GND
PGND
ISP ISN CSP 6.8nF CSS 47nF RZ3 2.55K CS 0.1uF
COMP CP1 15 pF
VFB
SS
R1 68.1K, 1%
CZ3 220pF CF1 22pF CZ2 390pF RZ2 37.4K
R2 54.9K, 1%
Figure 12. SP6133: 3.3V Input Buck Regulator with auxiliary 5V
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SP633 Synchronous Buck Controller
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APPLICATION INFORMATION
VIN
C5 0.1uF R4 10 Ohm DBST BAT54WS C1 68uF CBST 0.1uF VIN VCC R3 10K POWERGOOD PWRGD UVIN EN ENABLE BST GH SWN INTER-TECHNICAL, SC4015-1R2M 1.2uH, 17A, 4.37mOhm MB, Si4304DY 3.7 mOhm, 30V MT, Si4304DY 3.7 mOhm, 30V C2 68uF C3 68uF
4.5-5.5V
CVCC 10uF
GND
VOUT
C4 68uF
SP6133
GL
RS1 5.11K
RS2 5.11K
GND
3.3V 0-10A GND
PGND
ISP ISN CSP 6.8nF CSS 47nF RZ3 2.87K CS 0.1uF
COMP CP1 22 pF
VFB
SS
R1 68.1K, 1%
CZ3 180pF CF1 22pF CZ2 560pF RZ2 22.6k
R2 21.5K, 1%
Figure 13. SP6133: 5V Input Buck Regulator
VIN
C5 0.1uF DBST CVCC 10uF BAT54WS VIN VCC R3 10K POWERGOOD PWRGD UVIN EN ENABLE BST GH SWN INTER-TECHNICAL, SC4015-R75M 0.75uH, 20A, 3.25mOhm MB, Si4304DY 3.7 mOhm, 30V CBST 0.1uF MT, Si4304DY 3.7 mOhm, 30V
VAUX=12V
C1 100uF
C2 100uF
3-3.6V
GND
VOUT
C3 68uF C4 68uF
SP6133
GL
RS1 5.11K
RS2 5.11K
GND
1.8V 0-10A GND
PGND
ISP ISN CSP 6.8nF CSS 47nF RZ3 2.55K CS 0.1uF
COMP CP1 15 pF
VFB
SS
R1 68.1K, 1%
CZ3 220pF CF1 22pF CZ2 390pF RZ2 37.4K
R2 54.9K, 1%
Figure 14. SP6133: 3.3V Input Buck Regulator with auxiliary 12V bias
Oct 24-06 Rev L
SP633 Synchronous Buck Controller
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APPLICATION INFORMATION
VIN
C5 0.1uF DBST CVCC 10uF BAT54WS VIN VCC R3 10K POWERGOOD NC PWRGD UVIN EN ENABLE BST GH SWN SC5018-2R7M 2.7uH, 15A, 4.1mOhm MB, Si4320DY 4 mOhm, 30V CBST 0.1uF MT, Si4394DY 9.75 mOhm, 30V C1 22uF C2 22uF
10-15V
GND
VOUT
C3 100uF C4 100uF
SP6133
GL
RS1 5.11K
RS2 5.11K
GND
3.3V 0-10A GND
PGND
ISP ISN CSP 6.8nF CSS 47nF RZ3 1K CS 0.1uF
COMP CP1 39 pF
VFB
SS
R1 68.1K, 1%
CZ3 560pF CF1 22pF CZ2 1500pF RZ2 23.2K
R2 21.5K, 1%
Figure 15. SP6133: 10-15V Input Buck Regulator
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SP633 Synchronous Buck Controller
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PACkAGE: 16 PIN QFN
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SP633 Synchronous Buck Controller
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ORDERING INFORMATION
Part Number Temperature Range Package
SP633ER ........................................... ....-40C to +85C .......................................... 6 Pin QFN SP633ER/TR ..................................... ....-40C to +85C ...........................................6 Pin QFN
Availableinleadfreepackaging.Toorderadd"-L"suffixtopartnumber. Example:SP6133ER1/TR=standard;SP6133ER1-L/TR=leadfree /TR = Tape and Reel Packquantityis2500for QFN.
Solved by
Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL:(408)934-7500 FAX:(408)935-7600
TM
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Oct 24-06 Rev L
SP633 Synchronous Buck Controller
(c) 2006 Sipex Corporation
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